1. Field
Some example embodiments relate to a memory device and a method of manufacturing the same, and more particularly, to a memory device including a buried channel array transistor (BCAT) and a method of manufacturing the same.
2. Description of the Related Art
As recent memory devices have been highly integrated, the width and gap distance of line patterns in a cell transistor have been reduced and thus the channel length of the transistor has been shortened. When the channel length is decreased to be shorter than an effective channel length for the operation of the transistor, the electronic characteristics of the transistor are deteriorated due to the short channel effect.
For those reasons, a recess-channel transistor or a buried-channel array transistor (BCAT) have been provided for sufficiently increasing the channel length. Particularly, the BCAT can be manufactured to have 6F2-structured word lines in such a configuration that the pitch of the word lines is reduced to about 0.5 F, which can minimize or reduce the occupation of the BCAT in each cell of the memory device. Thus, the BACT has been used in recent memory devices from the viewpoints of channel increase and size reduction of the memory device.
According to the conventional 6F2-structured BCAT, voids frequently occur in the device isolation layer along a minor axis of the active region and the voids are usually filled with conductive materials of the buried gate structure, thereby forming conductive residual fillers in the device isolation layer. The conductive residual fillers usually function as a leakage path for leakage currents in the device isolation layer.